1. Technical Field
The present invention relates to an analog-to-digital converter (ADC), and more particularly, to a pipelined multi-stage ADC having an improved linearity and yield by using the proper combination of a binary-weighted capacitor (BWC) array and a unit capacitor (UC) array.
2. Background Art
Modern advanced electronic circuitry such as employed in a scanner, a high-definition television, a camcorder, a medical image processor and a radar system require availability of high resolution, high accuracy, excellent linearity, and high speed ADCs. Since a monolithic integrated circuit consumes relatively low power and occupies small area, a pipelined multi-stage ADC has been widely used for high speed analog-to-digital conversion. Examples of these types of ADCs are described, for example, in "A Fully Parallel 10-Bit A/D Converter With Video Speed" by Toyoki Takemoto et al., IEEE Journal of Solid State Circuits, vol. SC-17, no. 6, pp. 1133 to 1138 (December 1982), "An 8-MHz CMOS Subarranging 8-Bit A/D Converter" by Andrew G. F. Dingwall et al., IEEE Journal of Solid-Stage Circuits, vol. SC-20, no. 6, pp. 1138 to 1143 (December 1985), and "A Pipelined 5-Msample/s 9-bit Analog-to-digital Converter" by Stephen H. Lewis et al., IEEE Journal of Solid-Stage Circuits, vol. SC-22, no. 6, pp. 954 to 961 (December 1987). The parallel architectures require a large number of comparators, making their use for higher resolution impractical. The multistage conversion architectures reduce the total number of comparators significantly, resulting in a smaller chip area and lower power dissipation.
Conventional pipelined ADCs are disclosed in U.S. Pat. No. 4,745,394 for Pipeline A/D Converter issued to Cornett, and in U.S. Pat. No. 5,274,377 for Pipeline A/D Converter issued to Matsuura et al. In these conventional pipelined ADCs, a plurality of stages is employed wherein each stage initially samples and holds the output signal of the preceding stage and then performs a low resolution A/D conversion using a flash A/D converter on the held signal. The digital code produced is converted back to an analog signal by a digital-to-analog (D/A) converter and subtracted from the held signal to produce a residue that is amplified and passed to the next stage. Although this pipelined architecture offers an advantage of low hardware cost, it, however, suffers limited processing speed and accuracy.
Other conventional pipelined ADC designs having high processing speed are disclosed in U.S. Pat. No. 4,903,026 for Architecture For High Sampling Rate, High Resolution Analog-To-Digital Converter issued to Tiemann et al., and in U.S. Pat. No. 4,894,657 for Pipelined Analog-To-Digital Architecture With Parallel-Autozero Analog Signal Processing issued to Hwang et al., and in U.S. Pat. No. 5,403,732 for Analog-To-Digital Converter Employing A Pipeline Multi-Stage Architecture issued to Robertson. Generally, in these high speed multi-stage pipelined ADCs, high speed and low resolution flash ADC is used in each stage. The use of the low resolution flash ADC in the pipelined architecture although reduces the number of capacitors, however, consumes high power and requires high input capacitance, and consequently is limited to applications of less than ten-bit resolution. Moreover, each stage of the pipelined ADCs requires a sample-and-hold circuit to perform the analog-to-digital conversion, which consequently increases the power consumption.
Also, the actual ADC has various error factors since the characteristics of the circuit elements and the matching characteristics between the circuit elements are not perfect. Such error factors are embodied as an offset error, a gain error, an integral non-linearity (INL) error, and a differential non-linearity (DNL) error. Offset error represents a deviation degree of a predetermined amount from an ideal transfer characteristic of the ADC. The gain error represents the difference between the slopes of the actual code characteristic and the ideal code characteristic. The integral non-linearity (INL) error represents the change of the transfer characteristic from a linear characteristic to a curve characteristic; that is, the transfer characteristic is not an ideal linear function. The differential non-linearity (DNL) error, on the other hand, represents the irregularity of the adjacent output value. Among the these errors, the DNL error can be checked by measuring the difference of the distance between adjacent codes. If the INL error, however, becomes large, missing code is generated in the analog-to-digital conversion.
To improve the linearity of the pipelined multi-stage ADCs to beyond the ten-bit resolution and other error factors, digital domain code error calibration technique has been developed and introduced in U.S. Pat. No. 4,894,656 for Self-Calibrating Pipelined Subranging Analog-To-Digital Converter Processing and in U.S. Pat. No. 4,894,657 for Pipelined Analog-To-Digital Architecture With Parallel-Autozero Analog Signal Processing, both issued to Hwang et al. Similarly, in U.S. Pat. No. 4,908,621 for Autocalibrated Multistage A/D Converter issued to Polordo et al. calibrates each stage of the pipelined multi-stage ADCs to maintain proper error correction levels during operation of the converter to minimize quantization errors due to component aging, temperature and other environmental effects. In these calibration techniques, although mismatched segment errors such as offset error and gain error are measured and corrected, the resulting ADC linearity is still affected.
Another recent calibration techniques are disclosed in "Digital-Domain Calibration of Multistep Analog-to-Digital Converters," IEEE Journal Solid-state Circuits, pp. 1679 to 1688 (December 1992), and "Interstage Gain Prorated Technique for Digital-Domain Multi-Step ADC Calibration," IEEE Transactions on Circuits and Systems, pp. 12 to 18 (January 1994), both papers by S. H. Lee and B. S. Song. In these techniques, only 2.sup.n-1 codes with 2.sup.n-1 bytes of memory are calibrated using the principle of code symmetry. Consequently, it suffers from a truncation error-doubling effect in the midpoint transition resulting in linearity degradation. Moreover, since one-sided codes are calibrated, the characteristics of the central linearity is not sufficiently acceptable.